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eor e x em44am1684lba jul. 2006 www .eor ex.c o m 256mb (4m 4bank 16) double da t a ra te 2 sdram features ? jedec s t a ndard vdd/vddq=1.8v 0.1v . ? all input s an d output s are com p atible wi th sstl_18 inte rface. ? fully dif f erential clo ck in p u t s (ck,/ck) operation. ? 4 banks ? posted cas ? burst lengt h: 4 and 8. ? programm a ble cas late n cy (cl): 3, 4 and 5. ? programm a ble additive l a tency (al ) : 0, 1, 2, 3 and 4. ? w r ite laten cy (wl) =re a d laten cy (rl) -1. ? read late n c y (rl ) = pro g ramm able a dditive laten cy (al) + cas laten cy (cl ) ? bi-directio n a l dif f erential dat a s t ro be (dqs). ? dat a input s on dqs cent ers whe n write. ? dat a output s on dqs, /dqs edge s wh en rea d . ? on chip dl l align dq, dqs and /dqs transition with ck transition. ? dm mask write dat a - in at the both risi n g and falling edge s of the dat a st robe. ? sequential & interleaved burst type available. ? of f-chip dri v er (o cd) impeda nce adju stment ? on die t e rmination (odt) ? auto refre s h and self re fresh ? 8,192 refre s h cy cle s / 64ms ? a v erage ref r esh perio d 7 . 8us at lower than t case 85 c, 3.9us a t 85c < t case Q 95c ? rohs co m p lian c e ? partial array self-refre sh (p asr ) ? high t e mpe r ature self-refresh rate e nable description the em4 4 am 1684 lba is a high spe ed dou b le date rate 2 (ddr2) synchrono us dram fab r icate d with ultra high pe rforma nce cmos pro c e s s cont ainin g 268,43 5,456 bit s whi c h o r gani zed as 4mbit s x 4 ban ks by 16 bit s . this synchronou s devi c e achieves high spee d doubl e-d a t a -rate transfe r rates of up to 667 mb/se c /pin (ddr2 - 66 7) f o r gen eral ap plicatio ns. the chip i s desi gne d to comply with the following key ddr2 sdram featu r es: (1 ) po ste d cas with additive laten c y , (2 ) write l a tency = re a d laten c y -1, (3) of f-chi p drive r (o cd) impedan ce adju s tment and on die t e rmination (4) n o rm al and wea k stren g th dat a output drive r . all of the control a nd address input s are synchro n ized with a p a i r of externa lly supplied dif f erential cl ocks. inp u t s are l a tch ed at the cro s s point of dif f erential clo c ks (ck risi ng an d /ck falling). all i/os are synchroni zed with a p a i r of bidire ction a l strob e s (dq s and /dqs) in a sou r ce synchro nou s fashio n. the addre s s bu s is u s ed to convey ro w , colum n and b ank a ddress i n formatio n in a /ras and /cas multiplexing style. the 512m b ddr2 devi c e operate s with a single power supply : 1.8v 0.1 v vdd and v d dq. a v ailable p a ckag e: tfbga-84ball (12. 5mmx10mm, 0.8mm x 0.8mm ball pitch ) . ordering information part no organiz ation max. fr eq package grade pb em44am16 8 4lba-5f 16m x 16 ddr2 -40 0 m h z 3 - 3 - 3 tfbga-8 4ba ll comm ercial free em44am16 8 4lba-37 f 16m x 16 ddr2 -53 3 m h z 4 - 4 - 4 tfbga-8 4ba ll comm ercial free em44am16 8 4lba-3f 16m x 16 ddr2 -66 7 m h z 5 - 5 - 5 tfbga-8 4ba ll comm ercial free note: s peed bin is in orde r of cl-trcd-t r p 1/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m * eorex re serves the righ t to change p r odu ct s o r spe c ificatio n with out notice. 2/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m pin assignment: to p vi e w 1 2 3 7 8 9 v d d n c v s s a v s s q / u d q s v d d q d q 1 4 v s s q u d m b u d q s v s s q d q 1 5 v d d q d q 9 v d d q c v d d q d q 8 v d d q d q 1 2 v s s q dq1 1 d d q 1 0 v s s q d q 1 3 v d d n c v s s e v s s q / l d q s v d d q d q 6 v s s q l d m f l d q s v s s q d q 7 v d d q d q 1 v d d q g v d d q d q 0 v d d q d q 4 v s s q d q 3 h d q 2 v s s q d q 5 v d d l v r e f v s s j v s s d l c k v d d c k e / w e k / r a s / c k o d t n c b a 0 ba 1 l / c a s / c s a 1 0 / a p a 1 m a 2 a 0 v d d v s s a 3 a 5 n a 6 a 4 a 7 a 9 p a1 1 a 8 v s s v d d a 1 2 n c r n c n c 84ball tfbg a / (12.5mm x 10mm x 1.2mm) not e : 1. vddl and vssdl are po w e r and ground for the dll. 2. in case of only 8 dqs out of 16 dqs are used, l d qs, ldqs b and dq0 ~ 7 must be us ed. 3/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m pin desc ription (simplified) pin name functio n j 8 , k 8 c k , / c k (sy s tem clock) ck and ck a r e differe ntial clo ck in puts. all addre s s a nd co ntrol input sig nal s are sampl ed on the crossi ng of the posi t ive edge of ck and ne gat ive edge of ck. output (re ad) data i s ref e ren c e d to the cro s sing s of ck and ck (both dire ct ions of cro ssi ng). l 8 / c s (chip selec t ) all comman d s are m a ske d when cs is registe r ed high. cs provide s for e x ternal ra nk sele ction o n systems with multiple ran k s. cs is con s id ere d p a rt of the com m and code. k 2 c k e (cloc k enabl e ) cke high acti vates and ck e low deactiv a tes internal clo ck si gnal s and d e vice i nput buffe rs and o u tput drivers. ta king cke lo w provide s pre c ha rge po we r-do wn and self- refre s h operation (al l ban ks idle ), or active power-do wn (ro w active in an y bank). cke is syn c h r on o u s for po wer down entry a nd exit and fo r self-refre sh entry. cke is asyn ch ron o us for se lf-refresh exit. cke must b e maintaine d hi gh thro ugh ou t read an d wri t e accesse s . input buffers, excludi ng ck , ck, odt and cke are disabled du ring powe r down. input buffers, excludi ng ck e are disable d durin g self-refre sh. m8,m3,m7,n2,n8, n3,n7,p2,p8,p3, m2,p7,r2 a0~12 (ad d res s ) provided the row a d d r e ss f o r active co m m and s and th e colum n address an d auto prech a rge bit for rea d /write com m and s to sele ct one lo cation out of the memory a r ray in the resp ective ban k. a10 is sa mpl ed duri ng a p r echa rge com m and to dete r mine wheth e r the p r echa rge appl ies to o ne b a n k (a 10 l o w) or all ba nks (a10 hig h ). if only one ba nk is to be p r ech a rg ed, the bank i s sele cted by ba0, ba1. the addre s s inpu ts also p r ovid e the op-cod e du rin g mode regi ster set co m m and s. l 2 , l 3 b a 0 , b a 1 (ba n k addre ss) ba0 - ba1 define to which ban k an active, read, writ e or precharge co mmand i s bei ng appli ed (f or 256 mb an d 512mb, ba2 is not appli e d ) . bank ad dre ss al so d e termines if the mode regi ster or extende d mode regi ster is to be acce ssed du ring a mrs or e m rs cy cle. k 9 o d t (on die t e r m ination) odt (re g iste red hig h ) en able s termin a t ion resi stan ce internal to the ddr2 sdram. whe n enabl ed, odt is applie d to each dq, udqs/udqs , ldqs/ldq s, udm, and ldm si gnal. the o d t pin will be igno re d if the exten ded mod e re gister (emrs ( 1)) is prog ram m ed to disabl e odt. k7, l7, k3 /ras, /cas, /we (comman d input s ) /ras, /cas and /we (alo ng with /cs) define the co mmand bei ng entere d . b7,a8,f7,e8 udqs,/udqs, ldqs,/ldqs (da t a s t rob e ) output with read data, inp u t with write data. edge-ali gned with re a d data, cente r e d in write dat a. ldqs corresp ond s to the data on dq0 - dq7; udqs corre s p ond s to the data on dq 8-dq1 5 . the data strobe s ldqs an d udqs may be use d in sin g le ended mo de or pai red with optional com p lementa r y si gnal s /ldqs and /udqs 4/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m to provide differential pai r signaling to the system duri ng both read s and writes. a n emrs(1 ) control bit ena bles o r disabl es all compl e me nta r y data stro be signal s. in this data sheet, "differential dqs si gnal s" refers to a10 = 0 of emrs (1) u s in g l d qs/ldqs a n d udqs/udqs . "single-end e d dqs si gnal s" refe rs to a10 = 1 of emrs(1 ) usi ng ldqs and udqs. b 3 , f 3 u d m , l d m (input dat a mask ) dm is an in pu t mask signal for write d a ta. input data is masked whe n dm is sampled high coin cide nt wi th that input data durin g a write a c ce ss. dm is sampl ed on both e d ges of dqs. although dm pins a r e inp u t only, the dm loading mat c hes the dq a nd dqs loadin g . g8,g2,h7,h3,h1, h9,f1,f9, c 8, c2,d 7,d3, d 1 , d9,b1,b9 d q 0~ 15 (da t a input/ o utpu t) dat a in put s a nd output s are on the sam e pin. a1,e1,j 9 ,m9, r1/ a3,e3,j 3 ,n1, p9 vdd/vss (po w e r supp ly /ground) vdd and vss are power s u pply for internal c i rc uit s . a9,c1,c3, c 7 , c9,e 9,g1,g3,g7, g 9/ a7,b2,b8,d2,d8,e 7,f2,f8,h2, h 8 vddq/vssq (dq po w e r s upply / dq gr ound) vddq and v ssq are po wer su pply for the output buf f e rs. j 1 / j 7 v d d l / v s s d l (dl l po w e r supply / dll ground ) vddl and v ssdl are po wer sup p ly for dl l circui t s j 2 v r e f (re f er enc e v o lt age) sstl_1.8 ref e ren c e voltag e a2,e2,l1,r3, r 7, r8 nc (no conn ection) no internal el ectri c al conn ection i s pre s ent . 5/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m absolute m aximum rating symbol item rating unit s v in , v out input, output v o lt age -0.5 ~ +2.3 v v dd , v ddq, powe r suppl y v o lt age -0.5 ~ +2.3 v v ddl, dll po we r supply v o lt ag e -0.5 ~ +2.3 v t op operating t e mperature ra nge 0 ~ +8 5 c t st g s t orage t e m peratu r e ran ge -55 ~ +10 0 c p d powe r di ssi p a tion 1 w i os short circuit curre n t 50 ma not e : cautio n exposi ng t he devi c e to stre ss ab ove thos e li sted i n absolute m a ximum ratings co uld cau s e pe rma nent dama ge. the device is not m eant to be operate d unde r con d i t ions out side the limit s de scrib ed in the ope rational se ction of this sp e c ificatio n. exposure to ab solute maxim u m rating con d itions for extended pe riod s may af fect de vice relia bility . capacitance (v cc =1.8v 0.1v , f=1m hz, t a =2 5c) symbol paramete r min. ty p . max. unit s c ck input ca p a cit ance of ck, /ck 1.0 - 2.0 pf cd ck input ca p a cit ance delt a of ck, /ck - - 0.25 pf c i input ca p a cit ance for othe rs: cke, address , /cs, /ras, /cas, /we 1 . 0 - 2 . 0 pf cd i input ca p a cit ance delt a for others - - 0.25 pf c io input/output ca p a cit a n c e dq, dm, d q s, dqs, rd qs, rdqs 3 . 0 - 4 . 0 pf c dio input/output ca p a cit a n c e delt a - - 0.5 pf recommended dc operating conditions (t a =0c ~85c) symbol paramete r min. ty p . max. unit s v dd powe r suppl y v o lt age 1.7 1.8 1.9 v v dddl powe r suppl y for dll v o lt age 1.7 1.8 1.9 v v ddq powe r suppl y for output v o lt age 1.7 1.8 1.9 v v ref input referen c e v o lt a ge 0.49* v ddq 0.5* v ddq 0.51* v ddq v v tt t e rminatio n v o lt age v ref - 0.04 v ref v ref + 0 . 0 4 v v id dc dif f erentia l input v o lt ag e 0.25 - v ddq +0. 6 v v ih input logi c hi gh v o lt ag e v ref +0.125 - v ddq +0. 3 v v il input logi c l o w v o lt a ge -0.3 - v ref - 0.125 v not e : * all volt ages referred to v ss . 6/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m recommended dc operating conditions (v dd =1. 8 v 0.1v , t a =0 c ~ 85 c) -3 5-5 - 5 -37 4-4 - 4 -5 3-3 - 3 symbol paramete r t e st conditions max. max. max. unit s i dd1 operating cu rre nt (no t e 1) burs t length=2, t rc t rc (min.), i ol =0ma , one ba nk a c t i ve 1 1 0 9 5 7 5 m a i dd2p precharge s t andby cur r e n t in power do wn mod e cke v il (max.), t ck =min 5 5 5 m a i dd2n precharge s t andby cur r e n t in no n-po we r do wn mod e cke v ih (min.), t ck =min, /cs v ih (min.) input sign als switching 5 0 4 0 3 2 m a i dd3p active s t andb y cur r e n t in power do wn m ode (a12 =0 ) cke v il (max.), t ck =min 2 0 1 7 1 4 m a i dd3p active s t andb y cur r e n t in power do wn m ode (a12 =1 ) cke v il (max.), t ck =min 7 5 5 m a i dd3n active s t andb y cur r e n t in no n-po we r do wn mod e cke v ih (min.), t ck =min, /cs v ih (min.) input sign als switching 5 5 4 2 3 5 m a i dd4 operating cu rre nt (burst mode ) (no t e 2) t ck t ck (min.), i ol =0ma , all banks acti ve 1 7 0 1 3 0 1 0 0 m a i dd5 refre s h cu rrent (burst mode ) (no t e 3) t rc t rfc (min.), all banks active 1 7 0 1 5 0 1 3 0 m a i dd6 self refres h current cke 0.2v 5 5 5 m a i dd7 operating cu rre nt all bank interl eave rea d 240 220 210 ma *all volt ages referen c e d to v ss . not e 1: i dd1 d epen ds o n ou tput loading a nd cy cl e rate s. (cl=cl mi n. al=0 ) not e 2: i dd4 d epen ds o n ou tput loading a nd cycl e rate s. input sign als switching . not e 3: min. of t rfc (auto refresh ro w cycle t i me s) i s sho w n at ac characte ri stics. recommended dc operating conditions (continued) symbol paramete r t e st conditions min. max. unit s i il input lea kag e curre n t 0 v i v ddq , v ddq =v dd all other pin s not unde r tes t = 0 v - 2 + 2 u a i ol output lea ka ge cu rrent 0 v o v ddq , d out is disa bl ed - 5 + 5 u a v oh high l e vel o u tput v o lt age i o = - 1 3 . 4 m a v tt +0. 6 03 v v ol low l e vel ou tput v o lt age i o =+13.4 m a v tt -0.6 03 v 7/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m block diagram 8/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m ocd default setting t a ble symbol paramete r min. ty p . max. unit s - o u t p u t imped a n c e 1 2 . 6 1 8 2 3 . 4 ? - pull-up / pull down mism atch 0 - 4 ? - output imped ance step size for ocd cali brati on 0 - 1 . 5 ? - o u t p u t s l e w r a t e + 1 . 5 - 5 . 0 v/ns ac operating t e s t conditions (v dd =1. 8 v 0.1v , t a =0 c ~85 c ) symbol item conditions vswing(max) input signal maximum pe ak to pea k swing 1.0 v slew input signals minimum sl e w rate 1.0 v/ns v ref input referen c e level 0.5*v ddq ac operating t e s t conditions(continued) symbol paramete r min. max. unit s v id ac dif f erentia l input v o lt ag e 0.5 v ddq +0. 6 v v ix ac dif f erentia l corss point input v o lt ag e 0.5*v ddq - 0.175 0.5*v ddq + 0.175 v v ox ac dif f erentia l corss point output v o lt ag e 0.5*v ddq - 0.125 0.5*v ddq + 0.125 v v ih input logi c hi gh v o lt ag e v ref + 0.25 - v v il input logi c l o w v o lt a ge - v ref - 0.25 v v oh high l e vel o u tput v o lt age v tt +0.6 0 3 - v v ol low l e vel ou tput v o lt age - v tt -0.6 0 3 v 9/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m ac operating t e st characteristics (v dd =1. 8 v 0.1v , t a =0 c ~85 c) -3 -37 -5 symbol paramete r min. max. min. max. min. max. unit s t dqck dq outp u t acce ss from clk,/clk -0.45 + 0.45 - 0 . 5 + 0 .5 - 0 . 6 + 0 . 6 ns t dqsc k dqs output a c cess time from clk,/clk - 0 . 4 + 0 .4 -0.45 + 0.45 - 0 . 5 + 0 . 5 ns t cl ,t ch cl lo w/high l e vel wid t h 0.45 0.55 0.45 0.55 0.45 0.55 t ck t ck clo ck c y c l e t i m e 3 8 3.75 8 5 8 n s t ds dq an d dm setup time 0.1 - 0.1 - 0.15 - ns t dh dq an d dm h o ld time 0.18 - 0.23 - 0.28 - ns t dip w dq an d dm i nput pul se wi d t h for each input 0.35 - 0 . 3 5 - 0 . 3 5 - t ck t hz dat a o u t high impedan ce ti me from clk,/clk - + 0 . 4 5 - + 0 . 5 - + 0 . 6 n s t lz dat a o u t low i m peda nce time from clk,/clk -0.45 + 0.45 - 0 . 5 + 0 .5 - 0 . 6 + 0 . 6 ns t dqsq dqs-dq ske w for a s sociat ed dq si gnal - 0.24 - 0 . 3 - 0 . 3 5 n s t qsh dat a h o ld ske w facto r - 0.34 - 0.4 - 0.45 ns t dqss w r ite c o mmand to firs t latchin g dqs transition -0.25 + 0.25 -0.25 + 0.25 - 0 . 2 5 + 0 . 2 5 t ck t dqsl ,t dq sh dqs lo w/hig h input pul se wid t h 0.35 - 0 . 3 5 - 0 . 3 5 - t ck t dsl ,t dsh dqs input va lid wind o w 0 . 2 - 0 . 2 - 0 . 2 - t ck t mr d mode regi ster set comm and cy cle t i me 2 - 2 - 2 - t ck t wp r e s w r ite preamb l e setup time 0 - 0 - 0 - ns t wp r e w r ite preamb l e 0.35 - 0 . 3 5 - 0 . 3 5 - t ck t wp s t w r ite po st am b l e 0 . 4 0 . 6 0 . 4 0 . 6 0 . 4 0 . 6 t ck t is addre s s/co ntrol input setu p time 0 . 2 - 0 . 2 5 - 0 . 3 5 - n s t ih addre s s/co ntrol input hol d time 0.28 - 0 . 3 8 - 0 . 4 8 - n s t rpre rea d pream b l e 0 . 9 1 . 1 0 . 9 1 . 1 0 . 9 1 . 1 t ck 10/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m ac operating t e st characteristics (continued) (v dd =1. 8 v 0.1v , t a =0 c ~85 c) -3 -37 -5 uni t symbol paramete r min. max. min. max. min. max. t rpst rea d post a m b l e 0 . 4 0 . 6 0 . 4 0 . 6 0 . 4 0 . 6 t ck t ras active to precha rge comm and pe riod 45 70k 45 70k 45 70k ns t rc active to active comma nd perio d 6 0 - 6 0 - 6 0 - ns t rfc auto refre s h ro w cycl e t i m e 1 0 5 - 1 0 5 - 1 0 5 - ns t rcd active to rea d or w r ite del ay 15 - 15 - 15 - ns t rp precharge co mmand p e rio d 1 5 - 1 5 - 1 5 - ns t rrd active bank a to b comma nd peri od 10 - 10 - 10 - ns t ccd colum n add ress to colum n address delay 2 - 2 - 2 - t ck t wr w r ite r e c o v e r y t i m e 1 5 - 1 5 - 1 5 - ns t dal auto pre-cha r ge write re co very + pre - charge time t rp+ t wr - t rp+ t wr - t rp+ t wr - t ck t xsrd exit self refre s h to re ad comman d 200 - 200 - 200 - t ck t xsnr exit self refre s h to non -rea d comm and 1 15 - 1 15 - 1 15 - ns t xard exit active power-d own mo de to rea d comm and (f ast exit) 2 - 2 - 2 - t ck t xard s exit active power-d own mo de to rea d comm and (sl o w exit) 7-al - 6 - a l - 6 - a l - t ck t xp exit pre-ch arge po wer-d o w n to any non-re ad co mmand 2 - 2 - 2 - t ck t wt r internal w r ite to read com m and d e lay 7 .5 - 7.5 - 10 - ns t rt p internal read to pre-cha r g e d e l a y 7 . 5 - 7 . 5 - 7 . 5 - ns t cke cke minimu m p u l s e wid t h 3 - 3 - 3 - t ck t wp d w r ite to pre-charg e delay (same ban k) wl+ bl/2 + t wr - wl+ bl/2 + t wr - wl+ bl/2 + t wr - t ck t rpd rea d to pre - charg e delay (same ban k) al+ bl/2+1 - al+ bl/2+1 - al+ bl/2+1 - t ck t oit ocd drive m ode outp u t de lay 0 12 0 12 0 12 ns t refi a v erage p e ri odic refre s h i n t e r v a l - 7 . 8 - 7 . 8 - 7 . 8 us 1 1 /29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m ac operating t e st characteristics (continued) (v dd =1. 8 v 0.1v , t a =0 c ~85 c) -3 -37 -5 uni t symbol paramete r min. max. min. max. min. max. t aond odt t u r n - o n d e l a y 2 2 2 t ck t aofd odt turn-of f delay 2.5 2.5 2.5 t ck t aon od t turn-on (n o t e 1) tac ( mi n ) tac ( ma x ) + 1 tac ( mi n ) tac ( ma x ) + 1 tac ( mi n ) tac ( ma x ) + 1 ns t aof od t turn-of f (note 2 ) tac ( mi n ) tac ( ma x ) + 0 . 6 tac ( mi n ) tac ( ma x ) + 0 . 6 tac ( mi n ) tac ( ma x ) + 0 . 6 ns t aonp d odt turn-on (pow er-down modes) tac ( mi n ) + 2ns 2t ck+ tac ( ma x ) + 1ns tac ( mi n ) + 2ns 2t ck+ tac ( ma x ) + 1ns tac ( mi n ) + 2ns 2t ck+ tac ( ma x ) + 1ns ns t aofpd odt turn-of f (powe r -do w n mode s) tac ( mi n ) + 2ns 2.5 tc k + tac ( ma x ) + 1ns tac ( mi n ) + 2ns 2.5 tc k + tac ( ma x ) + 1ns tac ( mi n ) + 2ns 2.5 tc k + tac ( ma x ) + 1ns ns t anpd odt to power down mode entry laten cy 3 - 3 - 3 - t ck t axpd odt po we r do wn exit latency 8 - 8 - 8 - t ck not e 1: odt turn on time min i s w hen the device leaves high im pedance and od t resist ance begins to turn on. odt tu rn on time max is w hen the odt resist ance is fully on. both a r e measure f r om taond. not e 2: odt turn of f time min is w hen the dev ice st art s to turn of f odt resist ance odt tu rn of f time max is w hen the bus is in high im pedance. both a r e measured f r om taofd. 12/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m simplified s tate diagram 13/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 1. command t r ut h t a ble cke command sy mbol n-1 n /cs /r a s /c a s /we ba 0 , ba 1 a 10 a 12~ a 0 ignore comma nd d e s l h x h x x x x x x no operation n o p h x l h h h x x x read r e a d h h l h l h v l v read w i th a u t o pre-ch arg e reada h h l h l h v h v wr i t e w r i t h h l h l l v l v w r ite w i th a u t o pre-ch arg e wri t a h h l h l l v h v bank a c ti v a te a c t h h l l h h v v v pre-ch a r g e se lect ban k p r e h h l l h l v l x pre-ch a r g e a l l ban ks p a l l h h l l h l x h x (ext.) mo d e r e g i ster set (e)m rs h h l l l l v v v h = hi gh leve l, l = low lev e l, x = high o r low level (don't ca re), v = v a lid da t a i nput 2. cke t r uth t a ble cke item comm and symbol n-1 n /cs /ras /cas /we addr . idle cbr r e fre s h comma nd ref h h l l l h x i d l e s e l f refres h e n t r y s e l f h l l l l h x l h l h h h x self refres h self refres h exit l h h x x x x h l h x x x x i d l e p o w e r do w n entry h l l h h h x l h h x x x x powe r do wn powe r do wn ex it l h l h h h x rem a r k h = high level, l = low level, x = high o r l o w level (don 't care ) 14/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 3. operative command t a ble cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop l h h h x n o p nop l h h l x t e r m nop l h l x ba/ ca/ a 10 re ad/w rit / bw illegal (n ot e 1) l l h h ba/ r a a c t bank a c tive,latch ra l l h l ba, a 1 0 pr e/pr e a nop (no t e 3) l l l h x ref a auto refres h (note 4 ) idle l l l l op-code, mode-add mrs mode regi ster h x x x x de s l nop l h h h x n o p nop l h h l ba/ ca/ a 10 read/r ead a begin re ad,l a tch ca, determine a u t o-precharge l h l l ba/ ca/ a 10 writ/writ a begin write,l a tch ca, determine a u t o-precharge l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a precharge/prech a rg e all l l l h x ref a illegal ro w active l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m t e rminal b u rst l h l h ba/ ca/ a 10 read/r ead a t e rminate b u rst,latch ca, begin ne w re ad, determine au to-precharge l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba, a 1 0 pr e/pr e a t e rminate b u rst, prech a re l l l h x ref a illegal read l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m illegal l h l h ba/ ca/ a 10 read/r ead a t e rminate b u rst with dm =?h?,lat ch ca,begin re a d ,determine auto-p r e c h a rge (note 2) l h l l ba/ ca/ a 10 writ/writ a t e rminate b u rst,latch ca,begin new write, de termine auto-p r e c h a rge (note 2) l l h h ba/ r a a c t illegal (n ot e 1) l l h l ba, a 1 0 pr e/pr e a t e rminate burs t with dm= ? h?, precharge l l l h x ref a illegal wr i t e l l l l op-code, m r s illegal 15/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 3. operative command t a ble (continued) cur r e n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l ba/ ca/ a 10 t e r m illegal l h l x ba/ r a re ad/w rit e illegal (n ot e 1) l l h h ba/ a 1 0 a c t illegal (n ot e 1) l l h l x pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal read w i th ap l l l l op-code, mode-add mrs illegal h x x x x de s l nop(co ntinu e burst to end ) l h h h x n o p nop(co ntinu e burst to end ) l h h l x t e r m illegal l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal w r ite w i th ap l l l l op-code, mode-add mrs illegal h x x x x de s l nop(idle af ter t rp ) l h h h x n o p nop(idle af ter t rp ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a nop(idle af ter t rp ) (no t e 3) l l l h x ref a illegal pre-charging l l l l op-code, mode-add mrs illegal h x x x x de s l nop( ro w a c tiv e af ter t rcd ) l h h h x n o p nop( ro w a c tiv e af ter t rcd ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/write illegal (n ot e 1) l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal ro w activating l l l l op-code, mode-add mrs illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge 16/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 3. operative command t a ble (continued) curre n t s t ate /cs /r /c /w addr . comm and action h x x x x de s l nop l h h h x n o p nop l h h l x t e r m nop l h l h ba/ ca/ a 10 r e a d illegal (no t e 1) l h l l ba/ ca/ a 10 writ/writ a ne w write, d e termin e ap l l h h ba/ r a act illegal (n ot e 1) l l h l ba/ a 1 0 pr e/pr e a illegal (n ot e 1) l l l h x ref a illegal wr i t e recovering l l l l op-code, mode-add mrs illegal h x x x x de s l nop(idle af ter t rp ) l h h h x n o p nop(idle af ter t rp ) l h h l x t e r m nop l h l x ba/ ca/ a 10 read/w rit illegal l l h h ba/ r a act illegal l l h l ba/ a 1 0 pr e/pr e a nop(idle af ter t rp ) l l l h x ref a illegal refreshing l l l l op-code, mode-add mrs illegal rem a r k h = high level, l = lo w level, x = high o r l o w level (don 't care ), ap = auto pre-cha r ge not e 1: ille gal to ban k in spe c ified st ates; functio n may be legal in the ban k indicated by bank a ddre s s (ba), depe nding o n the st ate of that bank. not e 2: mu st satisfy bu s co ntention, bu s turn ar oun d, and/or write recove ry req u i r eme n t s . not e 3: nop to bank p r e c h a rgin g or in id le st ate.may pre c ha rg e ba nk indi cate d by ba. not e 4: ille gal of any bank i s not idle . 17/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 4. command t r ut h t a ble for cke cke curre n t s t ate n-1 n /cs /r /c /w addr . action h x x x x x x inv a lid l h h x x x x exis t self-ref resh l h l h h h x exis t self-ref resh l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop(maint a i n self refresh) h x x x x x x inv a lid l h h x x x x exis t power down l h l h h h x exis t power down l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal both bank precharge power do w n l l x x x x x nop(maint a in power down) h h x x x x x refer to func t i on true t able h l h x x x x enter po wer down mode (note 3 ) h l l h h h x enter po wer down mode (note 3 ) h l l h h l x illegal h l l h l x x illegal h l l l h h r a row ac tive/bank ac tive h l l l l h x enter self -ref r esh (note 3) h l l l l l o p-code mode regi ster access h l l l l l o p-code s pecial m ode registe r a c ce ss all banks idle l x x x x x x refer to c u rrent s t ate any s t ate oth er than listed ab ove h h x x x x x refer to com m and truth t a ble rem a r k : h = high level, l = low level, x = high o r l o w level (don 't care ) notes 1: af te r cke? s lo w to high tran siti on to exist sel f refresh mod e .and a time of t rc (min) has to be elap se af te r cke? s low to hig h tran sition to issue a n e w co mmand. notes 2: cke low to high transitio n is a synchrono us a s if rest art s in ternal cl ock. notes 3: p o wer do wn an d self refresh can be ente r e d only from the idle st ate of all banks. 18/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m initialization the followi ng sequ en ce is requi re d for p o we r-up an d initialization a nd is sho w n i n belo w figu re: 1. apply power and attemp t to maint a in cke below 0. 2 * vddq and odt at a lo w st ate (all other input s ma y be und efined ). t o guarante e odt of f, vref mu st be valid and a lo w level mu st be appli ed to the odt p in. - vdd,v d dl and vddq a r e driven from a singl e po we r conve r ter o u tput, and vtt is limited to 0.95 v max, and vre f tracks v d dq/2 or - apply vdd before o r at the sam e time as vddl; ap ply vddl before or at the s a me time as vddq; apply vddq before o r at the sam e time as vtt & vref . at least one o f these two set s of co nditi ons mu st be met. 2. s t art clock (ck, /ck) an d maint a in st able po we r a nd clo c k co nd ition for a min i mum of 200 s. 3. apply nop or de sele ct comman d s & t a ke cke high . 4. w a it minim u m of 400n s, then issue a precharge -all comma nd. 5. issue re se rved co mman d emrs(2 ) or emrs(3 ). 6. issue em rs(1) comma n d to enable dll. (a0=0 an d ba0=1 an d ba1=0) 7. issue m r s comma nd (m ode regi ster set) for "dl l reset". (a8=1 and ba0=ba 1 =0 ) 8. issue precharg e -all co mmand. 9. issue 2 o r more auto -refresh co mm and s. 10. issu e a m r s com m and with low on a 8 to initia lize device o peration. (witho ut resetting the dll ) 1 1 . at least 2 00 clo c ks af te r step 8, exe c ute ocd ca li bration (of f chip drive r im peda nce adju s tment). if ocd cali brati on is not u s e d , emrs ocd defa ult co mmand (a 9=a8=a7 = 1) foll owe d by emrs(1 ) o cd calib ration m ode exit com m and (a9 = a 8 =a7 = 0 ) must be issu ed wi th other p a ra meters of emrs(1 ). 12. the ddr2 sdram is now initiali ze d and re ady for no rmal op eration. 19/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m m o de register definition m o de register set the mod e re gister stores t he dat a fo r co ntrolling the v a riou s op erating mode s of dd r2 sd ra m whic h cont ain s add ressing mo de, burst len g th, /cas latency , wr (write re covery ), test mode, dl l re set and variou s vend or ? s spe c ific o p inion s . the default s valu es of the re gister i s not def ined, so the mode regi ster must b e written af te r po we r up fo r p r o p e r ddr2 s d ram ope ration . the mode registe r i s written by a s serti n g low on /cs, /ras, /cas, /we and ba0/ 1 . the st ate o f t he addre ss pins a0 -a12 i n the same cycle as /cs, /ras, /cas, /we and ba0, 1 going lo w is written in th e mode re giste r . t w o clo ck cycles a r e req ueste d to compl e te the write op eratio n in the mode registe r . the mode regi ster content s can be cha nge d usin g the same co mma nd and clo c k cycle req u ire m ent s du ring operating a s l ong a s all b a n ks are in the idle st ate. the mode regi ster is divided int o variou s fields de pen ding on function al ity . the burst length u s e s a0-a2, addressin g m ode u s e s a3, /cas latency ( rea d laten c y from colu mn address ) u s e s a4-a6. a7 i s used for test mode. a8 is use d for ddr reset. a9 ~ a1 1 a r e u s e d for write re covery time (wr) ,a7 must be set to low for normal m r s ope ration. with add re ss bit a12 two powe r-do wn mode s ca n b e sele cted, a ?st anda rd mode ? and a ?low-p ower? powe r-do wn mode. 20/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m address input for mode re gister set ( mrs ) ba1 ba0 a12 a1 1 a10 a9 a8 a7 a6 a5 a4 a 3 a 2 a 1 a 0 0 0 pd wr dll tm cas laten cy b t b u r s t le ngth dll re st a8 mode a7 b u r s t lt h a 2 a 1 a0 n o 0 n or mal 0 4 0 1 0 y e s 1 t e s t 1 8 0 1 1 activ e power - do wn mode a12 burst t y pe a3 fast ex it ( nor m al ) 1 s e q u e n t i a l 0 slow exit ( low power ) 0 i n t e r l e a v e 1 ba1 ba0 mrs mode 0 0 mode regi ster (m rs) 0 1 extended mo de re giste r / emrs(1 ) 1 0 emrs(2) * re serv e d 1 1 emrs(3) * re serv e d wr i t e r e c o v e r y a1 1 a10 a9 cas laten cy a6 a5 a4 re serve d 0 0 0 re serve d 0 0 0 2 0 0 1 re serve d 0 0 1 3 0 1 0 re serve d 0 1 0 4 0 1 1 3 0 1 1 5 1 0 0 4 1 0 0 6 1 0 1 5 1 0 1 re serve d 1 1 0 re serve d 1 1 0 re serve d 1 1 1 re serve d 1 1 1 21/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m burst t y pe (a3) burst le ngth a3 a2 a1 a0 sequential a ddre s sing interleave ad dre ssi ng x x 0 0 0 1 2 3 0 1 2 3 x x 0 1 1 2 3 0 1 0 3 2 x x 1 0 2 3 0 1 2 3 0 1 4 x x 1 1 3 0 1 2 3 2 1 0 x 0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 x 0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6 x 0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5 x 0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4 x 1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3 x 1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2 x 1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1 8 x 1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0 * page length is a function of i/o organi zation and col u mn add re ssi ng w r ite recovery wr (w rite recove ry) is fo r w r ite s with auto-pre ch arge only and d e fines the tim e whe n the dev ice st art s pre-cha r ge inte rn ally . wr mu st be prog ram m ed to match the minimum requi reme nt for the analo g ue twr timin g . power-down m ode active powe r -down (pd) m ode is d e fine d by bit a12. pd mode all o ws the u s e r to determi ne the active power-do w n mode, whi c h determi ne s p e rform a n c e vs. power savings. pd mo d e bit a12 doe s not apply to pre c ha rg e po wer-d o wn mo de. whe n bit a12 = 0, st a n dard a c tive powe r-do wn m ode or ?fa s t-e x it? active power-do w n mode is e nab led. the txard p a ramete r is u s ed for ?f ast-exit? a c tive power-do w n exit timing. the dl l is ex pecte d to be enabl ed and runnin g duri n g this mode. whe n bit m12 = 1, a lowe r powe r active powe r -do w n mode o r ?slo w-exit? a c tive power-do w n mode is enabl ed. the txards p a ra meter is u s e d for ?slow-exit ? active power-do w n exit timing. the dl l can b e enabl ed, but ?froze n? du ring active power-do w n mo de si n c e the exit-to-read co mmand timin g is relaxe d. the po we r dif f eren ce expe cted bet wee n pd ?normal ? and pd ?lo w-power ? mo de is define d in the idd t a ble. 22/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m 23/29 address input for extende d mo de register set ( emrs(1) ) the emrs (1 ) is written by asserting lo w on /cs, /ras, /cas, /we,ba1 and hig h on ba0 ( the ddr2 sho u ld be in all ban k pre - charg e with cke already prior to writin g into the extended mod e re giste r . ) the extende d mode re giste r emrs(1) st ore s the dat a for enabli ng o r disa bling th e dll, outp u t driver stren g th, addi tive latency , o cd p r og ram, odt , dqs an d output buf fe rs di sabl e, rqds and rdqs enable. the default value of the extended mo de regi ster em rs (1) is not de fined, therefo r e the extend ed mode regi ster mu st be written a f ter po we r-u p for prope r ope ration.th e mode re giste r set comma nd cycle time (tmrd) mu st be sati sfied to compl e te the write op er ation to the emrs(1 ). mode regi ster conte n t s can be cha nge d usi n g the same comman d and clo ck cycle re quire ment s d u ring n o rm al operation wh en all ban ks are in p r e-ch arge st ate. ba1 ba0 a12 a1 1 a10 a9 a8 a 7 a 6 a5 a4 a 3 a 2 a1 a0 0 1 q of f rdqs /dqs oc d prog ra m rtt a l r t t d.i.c dll q of f a12 1 / dqs a10 rtt a 6 a 2 dll rt a0 disable 0 enable 0 disabl e 0 0 enable 0 enable 1 disable 1 75 ? 0 1 disable 1 output 150 ? 1 0 buf fers 50 ? 1 1 rdqs, /rqds a1 1 i / o output driver impedence con t rol a1 disable 0 normal (1 00 %) 0 enable 1 onl y x 8 w e a k ( 60 %) 1 not e 1: whe n adjust m ode is issue d , al from p r ev iou s ly set v a lu e m u st b e ap p lied. not e 2: aft e r set t i ng t o de fa ul t , oc d m ode nee d s t o be exi t e d by set t i ng a 9 ~ a 7 t o 0 0 0 . refer t o the ch apter of f-c hip dri v er ( o cd ) im pedance a d j u st m e nt for det a i l e d i n f o rm at ion . ocd op eration a9 a8 a7 a dditive l a tency a5 a4 a3 ocd cali brati on mode exit 0 0 0 0 0 0 0 drive (1) 0 0 1 1 0 0 1 drive (0) 0 1 0 2 0 1 0 adjus t mode (no t e 1 ) 1 0 0 3 0 1 1 ocd cali brat ion default (n ote 2 ) 1 1 1 4 1 0 0 re serve d 1 0 1 re serve d 1 1 0 re serve d 1 1 1 ba1 ba0 mrs mode 0 0 mode regi ster (m rs) 0 1 extended mo de re giste r / emrs(1 ) 1 0 emrs(2) * re serv e d 1 1 emrs(3) * re serv e d
eor e x em44am1684lba jul. 2006 www .eor ex.c o m output drive s t rength the output d r ive strength i s define d by bit a1. norm a l drive stre ngt h output s are spe c ified to b e sstl_18. programmin g bit a1 = 0 sel e ct s no rmal ( 100 %) drive stren g th for al l output s. programmin g bit a1 = 1 will redu ce all o u tput s to ap proximately 60 % of t he sst l_18 d r ive strength. this optio n is intended for t he su ppo rt of the li ghter loa d and/or p o int - to-p oint environment s. single-ended and dif ferential data s t robe signals emrs s t obe fun c tio n matrix sign als a1 1 (rd q s enable) a10 (/dqs en able) rd qs dm /rdqs d qs /dqs 0 ( disable) 0 ( enable ) dm hi -z dqs / dqs d if ferential dqs signal s 0 ( disable) 1 ( disable) dm hi -z dqs h i -z singl e-e nde d dqs si gnal s 1 ( enable ) onl y for x8 0 ( enable ) rdqs /rdqs d qs /dqs dif f erential dqs signal s ( fo r x8) 1 ( enable) onl y for x8 1 ( disable) rdqs hi -z dqs h i -z singl e-e nde d dqs si gnal s ( for x8) output disable ( qof f ) und e r no rmal operatio n, the dram o u tp ut s a r e ena bl ed duri ng re ad ope ration f o r drivin g dat a (qof f bit in the emrs(1) is set to (0). when t he qof f bit is set to 1, the dram out put s will be disabled. di sabli ng the dram o u tput s allo ws u s e r s to mea s ure idd current s durin g re ad operation s , without inclu d in g the output buf fer current . 24/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m address input for extende d mo de register set ( emrs(2) ) * re serve d ba1 b a 0 a 1 2 a 1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a2 a1 a0 1 0 0 0 0 0 0 srf 0 0 0 0 p asr high t e mp erature self-re f resh rate en able a7 d i s a b l e 0 enable** (85 c t c a s e 95 c) 1 partial array self refres h a2 a1 a0 full array 0 0 0 half array (ba[1:0]=00&01 ) 0 0 1 quarte r array (ba[1:0]=00) 0 1 0 not define d 0 1 1 3 / 4 array ( b a [ 10 ] 0 1 1 0& 1 1 ) 1 0 0 half array (b a[1:0]=10&1 1 ) 1 0 1 quarte r a rray (ba[1:0]=1 1 ) 1 1 0 not define d 1 1 1 ba1 ba0 mrs mode 0 0 mode regi ster (m rs) 0 1 extended mo de re giste r / emrs(1 ) 1 0 emrs(2) * re serv e d 1 1 emrs(3) * re serv e d address input for extende d mo de register set ( emrs(3) ) * re serve d ba1 b a 0 a 1 2 a1 1 a 1 0 a 9 a 8 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 25/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m on-die t e rmination (odt) odt (on - di e t e rminatio n) i s a ne w featu r e on ddr2 compon ent s that allows a dram to turn on/of f terminatio n re sist an ce for e a ch udq, l d q, udqs, udqs, ldqs, ldqs, udm and ldm sig nal via the odt control pin for x16 configu r ation, whe r e udqs and l d qs are terminated only whe n ena ble d in the emrs(1) by addre s s bi t a10 = 0. the o d t feature is d e si gn ed to improve signal inte gri t y of the memory cha nnel b y allowing the dram controlle r to indep ende ntly turn on/of f terminatio n re si st an ce fo r an y or all dra m device s . the o d t fun c tion can be use d for all a c tive and st an dby mode s. odt i s turn e d of f and not sup porte d in self- r e fr es h mo de . odt function switch sw1 o r sw2 is en abl ed by the odt pin. selecti on between sw1 or sw2 is determi ned b y ?rtt (nomi nal)? in emrs(1 ) add ress bit s a6 & a2. t a rget rtt = 0.5 * rval1 or 0.5 * rva l 2. the odt pin will be ignored if the emrs (1) is programmed to disable odt . 26/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m of f-chip driver (o cd) impedance adjustment dr2 sdram supp ort s driv er cali brat ion feature an d the flow chart belo w is an e x ample of the sequ en ce. every calibration mode co mmand sho u l d be followed by ?ocd cali bration m ode exit? before a n y other comm and b e i ng issue d . mrs sho u ld be set before en tering o cd i m peda nce ad justment an d odt (on di e t e rminatio n) sho u ld be carefully controll ed dep endin g on system e n vironm ent. 27/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m ocd impedance adjust t o adjust output driver impedan ce, cont rollers must is sue the adjust emrs(1) comm and alo ng with a 4 bit burst code to ddr2 sdram as in the followin g t able. for this ope ra tion, burst length has to be set to bl = 4 via mrs com m and befo r e activating o c d and control l ers m u st d r ive the burst co de to all dq s at the same time. dt0 is the t able me a n s all dq bit s at bit time 0, dt1 at bit time 1, and so fo rth. the drive r output impeda nce is adjuste d for all ddr2 sdram dq s si mult ane ou sly and af ter o c d cali bratio n, all dq s of a given ddr2 sdram will b e adju s ted to the same d r iv er strength se tting. the maximum step count for adju s tment can be up to 1 6 and when t he limit is rea c he d, further i n creme n t or decrem ent co de ha s no ef fect. the de fault setting may be any step within the maximum st ep co unt ran g e . when adj u st mode comm and i s issued, al fro m previou s ly set value mu st be appli ed. of f-chip-driver adjust program 4 bit burst co de input s to a ll dqs operation d t0 d t1 d t2 d t3 pull-up d r iver strengt h pull-do wn d r i v er stre ngth 0 0 0 0 nop (n o ope ration ) n o p (n o ope ration ) 0 0 0 1 incre a se by 1 s t e p nop 0 0 1 0 de cre a se b y 1 s t e p nop 0 1 0 0 nop incre a se by 1 s t e p 1 0 0 0 nop de cre a se b y 1 s t e p 0 1 0 1 incre a se by 1 step incre a se by 1 step 0 1 1 0 de cre a se by 1 step incre a se by 1 step 1 0 0 1 incre a se by 1 step de cre a se by 1 step 1 0 1 0 de cre a se by 1 step de cre a se by 1 step other combi nation s re serve d re serve d 28/29
eor e x em44am1684lba jul. 2006 www .eor ex.c o m package description ( bg a - 8 4 b a lls pack ag e) 29/29

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